(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate complementary metal oxide semiconductor, (CMOS), device, featuring dual gate structures, such as a metal gate as well as a metal-polysilicon gate, on an underlying high dielectric constant, (high k), gate insulator layer.
(2) Description of Prior Art
Integrated circuit, (IC), technology has progressed to the point in which two different gate insulator thicknesses have been used to create CMOS devices with two different threshold voltages, allowing different, desired operating voltages to be realized for each CMOS device. Subsequent CMOS development featured gate structures, each comprised of a specific metal, on an underlying high k gate insulator, with each CMOS device resulting in a specific threshold, or operating voltage, realized via the difference in work function supplied by each specific metal. However the use of two different metal gate structures results in an increase in process complexity, as well as an increase in fabrication costs. In addition the use of polysilicon gate structures, on various thicknesses of underlying gate insulator layer, can result in CMOS device depletion effects resulting especially from N type implanted, polysilicon gate structures, when formed on thin silicon dioxide gate insulator layers.
This invention will describe a novel fabrication procedure for CMOS devices, in which dual gate structures, a metal gate, as well as a metal-polysilicon gate structure, are formed on an underlying high k gate insulator layer, resulting in a specific threshold voltage for each specific gate structure. Prior art, such as Liao et al, in U.S. Pat. No. 5,480,839, describe a method of fabricating CMOS devices that operate at different voltages, resulting from the use of doped, as well as undoped, polysilicon gate structures. However that prior art does not describe the unique process sequence of the present invention, in which metal gate structures, as well as metal-polysilicon gate structures, are formed on an underlying, thin high k gate insulator layer allowing a specific operating voltage to be realized for a CMOS device, as a function of structure type.